The present invention relates to a method of operating a nonvolatile memory device and, more particularly, to a nonvolatile memory device and a method of operating the same, in which program verify times can be controlled according to ambient temperatures.
A flash memory device, being a nonvolatile memory device, generally includes a plurality of strings in each of which a plurality of memory cells is connected in series. Flash memory devices have been widely used for various semiconductor devices such as portable electronic devices, such as notebook computers, personal digital assistants (PDAs) and mobile phones, computer bios, printers, and universal serial bus (USB) drivers.
A memory cell array of a general flash memory device has a structure in which memory cells are connected in series between bit lines BL and a cell source line CSL. Further, a NAND flash memory device has two transistors, such as a drain select line DSL and a source select line SSL, connected thereto in order to electrically connect the memory cell to the bit line BL and the cell source line CSL.
In addition, nonvolatile memory devices have increasingly adopted products using a multi-level cell (MLC), which is able to store several bits of data in one memory cell, in order to extend the capacity of data that can be stored. The nonvolatile memory device adopting the MLC has an increased capacity since several bits of data can be stored in one memory cell. However, in this nonvolatile memory device, in the case in which one memory cell is programmed, a threshold voltage distribution is divided into several voltage distributions. Thus, the width of the threshold voltage distribution has to be narrowed through programming so as to reduce error at the time of data reading.
In order to reduce the width of the threshold voltage distribution, a variety of programming methods have been presented. One of the methods can include a method of performing a verify operation in several levels by subdividing a verify voltage with respect to one threshold voltage distribution.
However, to verify one threshold voltage distribution in several verify voltage levels is problematic in that the program time is increased. Accordingly, a fast verify method has been used which can shorten the program time while employing several verify voltage levels.
FIG. 1 is a diagram showing voltage levels for the fast verify method in threshold voltage distributions.
Referring to FIG. 1, if it is sought to include memory cells of a first threshold voltage distribution 110, including erase cells, in a second threshold voltage distribution 120 through programming, four verify voltage levels PV11 to PV14 are used.
Here, the fast verify method is used. The fast verify method is a method of precharging a bit line only once and then performing a verify operation while sequentially changing a verify voltage. In other words, after the bit line is precharged only once, the four verify voltages PV11 to PV14 are sequentially applied to a selected word line.
If the fast verify method is used as described above, a verify operation with several levels can be performed on one threshold voltage distribution. Consequently, the verify time can be shortened while narrowing the width of the threshold voltage distribution.
However, the fast verify method may become problematic when there is a lot of the leakage current in a bit line. The leakage current of a bit line increases when temperature rises according to the characteristics of a nonvolatile memory device. Due to this, even though a cell is in a pass state, the cell can be recognized as a failure since a bit line voltage is lowered due to the leakage current. In this case, an over program can be performed since the program is continuously performed.